1. Field of the Invention
Embodiments of the present invention relate to semiconductor fabrication, and in particular, to methods for reducing the width of MOSFET gate structures.
2. Related Art
The demand for increased performance and greater functionality in semiconductors has driven the semiconductor industry to develop processes that pack more and more devices onto a substrate to create higher device densities. One approach to packing more devices onto a substrate is to shrink the size of the individual devices and their components. For example, a MOSFET may be made to operate faster by reducing the width of the gate line that drives it's gate, and hence the channel width of the device.
Improving the lithographic techniques that are used to define device patterns is one focus of this approach. Conventional photolithography techniques such as projection lithography define devices by transferring their patterns to a photoresist material that is coated on a semiconductor substrate. Using a series of optics, an image of a pattern representing an integrated circuit device is projected onto the photoresist. Current projection lithography is able to reduce critical geometries of the projected images to approximately 100 nm. However, because the demand for higher packing densities and increased performance requires that MOSFET gate widths be reduced below 100 nm, to 50 nm or less, conventional projection lithography techniques for gate formation will soon be inadequate.
Accordingly, recent approaches to further reduction of device dimensions have focused on supplementing conventional projection lithography techniques through additional photoresist processing. One such technique involves trimming a photoresist mask by isotropic etching to reduce the size of the mask beyond the minimum size achievable through projection lithography. An example of this technique is illustrated in FIG. 1. As shown in FIG. 1, a photoresist mask 2 form defining the shape of a MOSFET gate is formed by projection lithography over a multi-layered structure that includes an antireflective (ARC) layer 4, a gate conductive layer 6 formed of polysilicon, and a gate insulating layer formed of SiO2. The multi-layered structure is formed over a semiconductor substrate 10 that includes field isolations 12 that define the boundaries of MOSFET source and drain regions. For purposes of this example, it is assumed that the photoresist mask 2 has the minimum width achievable through projection lithography alone. It can be seen in FIG. 1 that through subsequent anisotropic etching using the photoresist mask 2 as an initial etch mask, the width of structures formed by etching the conductive gate material 6 and gate insulator 8 will be limited to the width of the photoresist mask 2. However, in accordance with the gate trim technique, the photoresist mask 2 is subjected to an isotropic etch that removes photoresist material, leaving a trimmed photoresist mask 14. The trimmed photoresist mask 14 is then used to pattern the underlying layers, resulting in a gate that has a width that is less than the minimum width achievable through projection lithography.
The resist trim technique is limited by the fact that a minimum thickness of photoresist is required in order to successfully transfer the shape of the photoresist mask to underlying layers. Accordingly, the improvements in gate size provided by the resist trim technique are also limited.
Consequently, there is a need for further techniques for providing further reductions in gate widths.